High performance microprocessor, microcontroller and communication chips require very high speed interconnects between the active transistor devices which are used to perform the various functions such as logical operations, storing and retrieving data, providing control signals and the like. With the progress in the transistor device technology leading to the present ultra large scale integration, the overall speed of operation of these advanced chips are beginning to be limited by the signal propagation delay in the interconnection wires between the individual devices on the chips. The signal propagation delay in the interconnects is dependent on the RC product where R denotes the resistance of the interconnect wires and C represents the overall capacitance of the interconnect scheme in which the wires are embedded. Use of copper instead of Al as the interconnect wiring material has allowed the reduction of the resistance contribution to the RC product. The current focus in the microelectronics industry is to reduce interconnect capacitance by the use of lower dielectric constant (k) insulators in building the multilayered interconnect structures on chips.
One prior art method of creating interconnect wiring network on such small a scale is the dual damascene (DD) process schematically shown in FIG. 1. In the standard DD process, an inter metal dielectric (IMD), shown in FIG. 1a as two layers 1110, 1120 is coated on the substrate 1100. The via level dielectric 1110 and the line level dielectric 1120 are shown separately for clarity of the process flow description. In general, these two layers can be made of the same or different insulating films and in the former case applied as a single monolithic layer. Historically, both layers are made from an inorganic glass like silicon dioxide (SiO2) or a fluorinated silica glass (FSG) film deposited by plasma enhanced chemical vapor deposition (PECVD). A hard mask layer or a layered stack 1130 is optionally employed to facilitate etch selectivity in the subsequent patterning steps and to serve as a polish stop. The wiring interconnect network consists of two types of features: line features that traverse a certain distance across the chip, and the via features which connect lines in different levels of interconnects in a multilevel stack together.
In the dual damascene process, the position of line 1150 and a via 1170 is defined lithographically in an example of a “line-first” approach. Lithography is used to define a trench pattern 1150 in photoresist 1500 (FIG. 1b) and a via pattern 1170 in photoresist layer 1510 (FIG. 1c) and the pattern is transferred into the dielectric material to generate a via opening 1180, FIG. 1d. The dual damascene trench and via structure 1190 is shown in FIG. 1e after the trench has been etched and the photoresist has been stripped. This recessed structure 1190 is then coated with a conducting liner material or material stack 1200 that serves to protect the conductor metal lines and vias and functions as an adhesion layer between the conductor and the IMD. This recess is then filled with a conducting fill material 1210 over the surface of the patterned substrate. The fill is most commonly accomplished by electroplating of copper although other methods such as chemical vapor deposition (CVD) and other materials such as Al or Au can also be used. The fill and liner materials are then chemical-mechanical polished (CMP) to be coplanar with the surface of the hard mask and the structure at this stage is shown in FIG. 1f. A capping material 1220 is deposited as a blanket film, as is depicted in FIG. 1g to passivate the exposed metal surface and to serve as a diffusion barrier between the metal and any additional IMD layers to be deposited over them. Silicon nitride, silicon carbide, and silicon carbonitride films deposited by PECVD are typically used as the capping material 1220. This process sequence is repeated for each level of the interconnects on the device. Since two interconnect features are simultaneously defined to form a conductor inlaid within an insulator by a single polish step, this process is designated a dual damascene process.
In order to lower the capacitance, it is necessary to use lower k dielectrics such as organic polymers, low k PECVD films containing Si, C, O and H and spin on organo-silicate glasses which have k values in the 2.5 to 3.0 range instead of the PECVD silicon dioxide based dielectrics (k=3.6 to 4.0). The k value can be further reduced to 2.2 (ultra low k) and even below 2.0 (extreme low k) by introduction of porosity in these insulators. For the purpose of brevity, we shall refer to these ultra low k and extreme low k materials collectively as very low k materials in this document. Although a tunable range of k values is possible with this set of very low k materials there are several difficulties in integrating these materials with copper interconnects by the dual damascene process described above.
First, these low k dielectrics have a much lower elastic modulus, fracture toughness and cohesive strength than the silicon dioxide or FSG films and their adhesion to typical hard mask layers used in current state of the art copper interconnect is also correspondingly inferior. As a result, when the CMP of the copper fill is attempted during the dual damascene interconnect build, delamination occurs either cohesively in the weak low k material or adhesively at the interface between the very low k material and the hard mask. This renders the DD process highly impractical from the point of view of manufacturability and yields.
Second, most of the very low k films, in particular the ones that are organosilicate-based, are very sensitive to plasma exposures because of the relative ease of oxidation or cleavage of the Si-organic group linkage (for example, Si-methyl) which results in sites that react with moisture in the ambient to form silanol (Si—OH) groups in the film. Silanols absorb H2O and hence increase the dielectric constant and the dielectric loss factor of the film significantly thus negating the performance benefits expected from the very low k films. Since reactive ion etch and plasma etch are key steps required in the formation of the dual damascene trench and via structure as described above and in the removal of photoresists used in patterning the very low k materials, it is very difficult if not impossible to avoid plasma damage of this class of films during a prior art dual damascene integration.
Third, many of the organosilicates tend to react with the highly sensitive photoresist layers used to define the fine interconnect pattern leading to a deterioration of the imaging and resolution capability of the resists. This phenomenon referred to as photoresist poisoning is further aggravated when lithography is attempted on a previously reactive ion etched surface of these dielectrics (as for example, during the lithography step to define via patterns in a photoresist coated over a previously reactive ion etched trench pattern in the low k dielectric film or vice versa).
Additionally, the material make up of the dual damascene interconnect structure significantly degrades the effective dielectric constant (keff). This is due to the presence of higher k hard mask layers and cap layers in the structure. Although, the effective k can be lowered using the very low k intermetal dielectrics (if they can be successfully integrated), the keff reduction achievable is limited by the presence of higher k dielectric layers typically used for the hard mask and the cap layer described in FIG. 1. Thus for example, when the k of the IMD is reduced from 2.65 to 2.2 (a 17% reduction in k), the keff is only reduced from 3.04 to 2.68 (only a 12% reduction) because of the effects of the contribution from these higher k layers. Another aspect of the prior art DD integration of very low k dielectrics is the use of optional reactive ion etch stop layers (not shown in FIG. 1) disposed between the dielectric layers 1110 and 1120. The function of this layer is to act as RIE stop between the two layers and hence allow better control of the etch depths and bottom surface topography of the line trenches. These etch stop layers also have a higher dielectric constant than the very low k dielectrics and hence further degrade the keff of the DD structures containing them. Further, the thickness of these hard mask, cap and etch stop layers do not scale proportionally with decreasing interconnect layer and IMD thickness expected in future generations. This is because the reliable functioning of these layers requires a minimum thickness that is independent of the IMD thickness. The result is that the detrimental effect of these high k layers is further aggravated at finer ground rules required for the future microelectronic interconnect structures.
One prior art approach that addresses some of the issues raised above is U.S. Pat. No. 6,146,986 by Wagganer. This patent teaches the use of photoresist as a temporary interlayer dielectric for the via openings and the line trenches, filling these with the metal and planarizing as in the standard dual damascene process as described above, stripping the photoresist all around the metal and filling all the spaces opened up between and underneath the metal features with the very low k dielectric films. Although this approach avoids the exposure of the very low k dielectric to the plasma processes, it will be exposed to some photoresist processing. Additionally, this process is not reliably manufacturable due to the fact that the lines are suspended using only the vias as support after the photoresist is stripped which will be extremely fragile to handle and are quite likely to deform when the supporting resist is being removed. Further, the fill process of the very low k dielectric has to fill under the lines in order to provide support and this is likely to be difficult to achieve. Even if this does occur the best final structure will only have the mechanically weak very low k dielectric everywhere around and under the lines and this will present delamination problems similar to the standard dual damascene polishing process, when the next level of interconnect is fabricated on top of the filled and planarized structure.
It is clear therefore that an alternate integration method is required to avoid the above stated problems associated with the prior art structures and achieve a mechanically robust and lower keff interconnect structure using very low k IMD materials.
There is a need to avoid damaging and increasing the dielectric constant of the very low k dielectric during the various processing steps employed. There is a further need to avoid the delamination of the structures during metal chemical-mechanical polishing steps. There is a further need to eliminate the possibility of photoresist poisoning problems stemming from its interactions with the very low k dielectric materials. Satisfaction of these needs is achieved by the inventive method described in detail below.